top of page
Prashant Mangal
Analog IC Designer
PROJECTS
Design of Wide Range DLL (300MHz-1.6GHz) with 32 Delay Taps for DDR applications
Design of Calibrated GPIO DDR3 Receiver operating upto 2400Mbps
Design of I-Order Continuous Time Delta Sigma ADC
Design of Low Jitter Clock Networks using Regulator
Design of Voltage Regulators
Design of Current Feedback VDSL2 Line Driver with speeds uotp 30MHz
Design of Variable Gain Amplifier from 20dB-50dB in Steps of 1dB with 900MHz Bandwidth
Design of Bandgaps & Temperature Sensor
Design of Clock Multiplier Unit (PLL) at 1.25GHz with 8 Phases
Design of Low Noise Trans-Impedance Amplifier for Optical Power Monitor
Design of Temperature Sensor, Programmable Amplifier and II Order Delta-Sigma ADC
Design of Switch Capacitor Filters using Multi Stage Opamps
bottom of page